`timescale 1ns/1ps

// The clock period is 25 MHz = 40 ns
`define TIMING_PERIOD 9.25925926

module tb_vga ();

reg clk;
reg rst_n;
reg blank;
reg border_en;
reg [7:0] border_width;
reg [7:0] border_color;
reg [7:0] bg_color;
wire [2:0] red;
wire [2:0] green;
wire [1:0] blue;
wire hs;
wire vs;

integer i;

initial begin
  $vcdpluson(tb_vga);
end

initial begin
  clk   = 0;
  rst_n = 0;
  blank = 0;
  border_en = 0;
  border_width = 8'd5;
  border_color = 8'b111_000_00;
  bg_color     = 7'h00_000_00;

  @(negedge clk);
  rst_n = 1;

  $display ("starting up");

  // Loop for 20 frames
  for (i = 0; i < 32'd20; i = i + 1) begin
    if (i == 32'd3) begin
      blank = 1;
      $display( "Blank enabled" );
    end else begin
      blank = 0;
    end

    if (i == 32'd5) begin
      border_en = 1;
      $display( "Border enabled" );
    end

    if (i == 32'd2) begin
      bg_color = 8'b001_001_01;
      $display( "Bg_color changed" );
    end

    @(posedge vs);
    $display("Line %d @ %t", i, $time);
  end


  $finish;
end

always #( `TIMING_PERIOD / 2 ) clk = ~clk;

vga_ctrl i_vga_ctrl (
  .clk(clk),
  .rst_n(rst_n),
  .blank(blank),
  .border_en(border_en),
 // .border_color(border_color[7:0]),
 // .border_width(border_width[7:0]),
  .bg_color(bg_color[6:0]),
  .red(red[2:0]),
  .green(green[2:0]),
  .blue(blue[1:0]),
  .vs(vs),
  .hs(hs)
);

endmodule
